# gevorg.fr


## Posts

- [CMOS AND3 Gate Design and Layout](https://gevorg.fr/cmos-and3-gate-design-and-layout/): Go to the GitHub repository This project focuses on the design and layout of a 3-input CMOS AND gate (AND3) using Cadence Virtuoso and the AMS 0.35 µm technology. The goal was to complete a full custom design flow — from schematic to post-layout simulation — and to analyze the impact of parasitics on timing performance. Project Workflow Schematic Design Created the logic structure using a NAND3 + Inverter implementation for efficiency. (See CMOS Inverter project) Pre-Layout Simulation Performed Simulations to ensure the logical functionality Layout design Built the physical layout of the NAND3 Gate in Virtuoso Layout‑XL using Euler paths to minimize diffusion breaks and area. Reused the existing CMOS Inverter layout from the previous project Verification Performed Design Rule Check (DRC) to ensure compliance with design rules. Conducted Layout Versus Schematic (LVS) to confirm consistency between schematic and layout. Extracted parasitics (PEX) and ran post-layout simulations to evaluate performance degradation caused by layout effects. Used Tools Cadence Virtuoso for schematic, simulation (ADE XL) , and layout (Layout XL) AMS 0.35 µm PDK (C35B4) CMOS technology SPICE simulations for electrical validation (DRC, and LVS) Layout Used the “Generate from Cellview” feature to automatically produce a layout template and speed up the process for the NAND3 Layout. Reused the existing inverter layout from a previous project to ensure consistency and save time. Used DRM to ensure size and design constraints respect Parasitic Extraction  Generated an extracted view including parasitics. Impact on performance There is a performance degradation due to parasitic capacitances We can see that the propagation delays are higher after Layout Pre-Layout : tpHL = 0.3115 ns Post-Layout : tpHL = 0.3654 ns
- [FPGA Design](https://gevorg.fr/fpga-design/): Go to the GitHub repository The goal of this project was to design and implement an FPGA-based system capable of processing an electrocardiogram (ECG) signal in real time. The main idea was to leverage the speed and parallelism of reconfigurable hardware to perform biomedical signal processing with security using ASCON128 encryption. Global view This diagram shows the data flow between a computer and an FPGA board for secure ECG signal transmission. On the computer side, ECG data stored in .csv files are sent to the FPGA via a UART interface. Once received, the FPGA processes the data and applies ASCON encryption, a lightweight cryptographic algorithm designed for secure communication. The encrypted signals are then transmitted back to the computer, where they are decrypted and displayed for real-time waveform monitoring, using Python libraries. Used Tools FPGA: Xilinx Pynq-Z2 board AMD Vivado: design and behavioral simulation Python with libraries : signal visualization and analysis
- [CMOS Inverter Design and Layout](https://gevorg.fr/cmos-inverter-design-and-layout/): Go to the GitHub repository The goal of this project was to design, simulate, and implement the physical layout of a CMOS inverter using Cadence Virtuoso. The project was carried out on the AMS 0.35 µm (C35B4) technology node, providing hands-on experience with an industry-grade process design kit (PDK). Project Workflow Schematic Design Built the inverter at the transistor level with NMOS and PMOS devices. Performed DC simulations to extract the Voltage Transfer Characteristic (VTC). Ran parameter sweep on MOS Width to optimize the inversion. Layout Implementation Designed the full custom layout of the CMOS inverter following AMS 0.35 µm design rules. Adjusted transistor sizing to balance performance and technology requirments. Verification Performed Design Rule Check (DRC) to ensure compliance with AMS design rules. Conducted Layout Versus Schematic (LVS) to confirm consistency between schematic and layout. Extracted parasitics (PEX) and ran post-layout simulations to evaluate performance degradation caused by layout effects. Used Tools Cadence Virtuoso for schematic, simulation (ADE XL) , and layout (Layout XL) AMS 0.35 µm (C35B4) CMOS technology SPICE simulations for electrical validation (DRC, and LVS) Layout Layers MET1, POLY1, NDIFF, NPLUS Used DRM to ensure size and design constraints respect
- [RTL Design & Verification](https://gevorg.fr/rtl-design-and-verification/): Go to the GitHub repository The goal of this project was to design and verify the ASCON128 cipher, a lightweight authenticated encryption algorithm (AEAD). The focus was on building a correct and modular RTL design in SystemVerilog and validating its functionality through behavioral simulation using ModelSim. System Architecture ASCON128 operates on a 320-bit internal state divided into five 64-bit words. The encryption process includes several phases: initialization, associated data processing, plaintext encryption, and finalization with authentication tag generation. To implement this algorithm in RTL, the project was divided into the following components: Constant Addition (PC) – injects round constants into the state during each round. Substitution Layer (PS) – applies parallel 5-bit S-box transformations. Diffusion Layer (PL) – spreads information across the state for proper mixing. Permutation Engine – executes sequences of 6 or 12 rounds, combining the above layers. XOR Modules & Registers – handle integration of keys, plaintext, and associated data. FSM (Finite State Machine) – controls the sequencing of operations (partially implemented for initialization).   The permutation core with all its components (constants, S-box, diffusion, XORs, and registers) was fully implemented and verified against reference values. Used Tools SystemVerilog for RTL design ModelSim for compilation and simulation of testbenches VS Code for source code management and organization

## Pages

- [Entrep Certification](https://gevorg.fr/entrep-certification/)
- [Python Certification](https://gevorg.fr/python-certification/)
- [TOEIC Certificate](https://gevorg.fr/toeic-certificate/)
- [My Resume](https://gevorg.fr/english-resume/)
- [Home](https://gevorg.fr/): Hi, I’m Gevorg ISHKHANYAN Master's Degree Graduate Microelectronics Engineer ASIC Designer Hardware enthusiast | Young engineering graduate, driven by self-improvement, curiosity, and learning. As a hardware enthusiast, I enjoy every part of the product creation, from marketing to design. Download Resume Request Call Request Call With Me Name Email Additional Comment Send Edit Template Who am I ? Driven by Curiosity, Powered by Engineering I am a passionate Microelectronics and Computer Engineering student with a strong interest in IC Design. I enjoy solving complex problems, learning new technologies, and turning abstract ideas into working projects. Curiosity and determination drive me forward. I believe failure is not the opposite of success but part of the journey. My goal is to contribute to impactful projects in the fields of semiconductors and hardware design, while constantly learning and improving. Education & Experience Engineering student Gevorg IshkhanyanAspiring  ASIC Designer Download Resume 2021 – 2026 (Graduating 11/2026)Ecole des Mines de Saint Etienne | Gardanne Master's degree in Microelectronics Design Specialized in microelectronics and computer science, I’m developing advanced skills in Analog and Digital IC design, FPGA and hardware architecture. This 5-year course provides training in both hardware and software. I choose a Major in Microelectronics Design Jan 2024 – Feb 2024Microchip Inc. | Rousset Analysis of MPU hardware competition (Intern) Analysis of the competition’s MPUs (microprocessors), comparing functionalities and ecosystem (software and hardware). Set up an MPU functionalities and target features comparator Excel tool, to support MPU Marketing team.Presentation of my study in English to my supervisors and the company’s marketing leads. Apr 2025 – Aug 2025Infineon Technologies | Villach (Austria) Automatizing FSM Development (Intern) Building a full design and verification environment for FSMs based on internal meta-model RTL generation flow. Collaboration with design and verification colleagues to collect specific requirements. Definition of suitable FSM architectures. Extension of the existing generation environment to build FSM architectures from a golden source. Apr 2026 – Sep 2026Kontron Modular Computers | Toulon Hardware Design Engineer (intern) In a high-standard industrial environment, I contribute to the design and development of a QMC-format (VITA 93.0) Chassis Manager board from start to finish. A comprehensive project (specifications, architecture, schematics, routing, testing) in an environment with strict technical constraints and norms to be compliant. See more on my GitHub page here My Projects Here are some projects I made during my studies or personal projects that are reflecting my skills and the types of projects I am working on. CMOS AND3 Gate Design and Layout FPGA Design CMOS Inverter Design and Layout RTL Design & Verification Hard Skills Cadence Virtuoso Hands-on experience in Cadence Virtuoso and ADE-XL and Layout-XL, performing simulations and analyses for analog and digital circuits. Analog Design and Layout (CMOS Technology) Knowledge of transistor-level design and layout using AMS 350 nm and TSMC 180 nm CMOS technologies. Designed and implemented core circuits such as inverters, current mirrors, and operational amplifiers. FPGA Design, AMD Vivado Proficient in FPGA design using AMD Vivado, with experience in implementing digital modules, on Xilinx hardware. RTL Design in SystemVerilog Practical expertise in SystemVerilog for RTL coding, simulation, and verification (ModelSim). Developed modules including ASCON128 encryption, finite state machines, and custom logic blocks. Analog and Digital Electronics Fundamentals Strong foundation in semiconductor physics, circuit analysis, and digital logic. Ability to design, simulate, and debug circuits from basic building blocks. Siemens EDA Hardware Schematic Design using Xpedition Design suite (Mentor Xpedition) Soft Skills Here are the technical and professional skills I have developed through my studies, projects, and internships. Project Management Teamwork Analytical Mindset Experienced in coordinating projects from start to finish, defining priorities, and ensuring timely delivery. Gained through student associations, robotics and entrepreneurship competitions , and internships. Strong ability to work in diverse and international teams and take initiatives. Managed a robotics team for the French Robotics Cup and acted as Technical Manager in a cybersecurity association. Skilled at analyzing complex problems and finding efficient, creative solutions. Applied in hardware design, FPGA development, and market analysis during internships. Languages French [ Native ] 0 % Armenian [ Native ] 0 % English [ C1 ] , TOEIC : 915/990 , Professional working proficiency 0 % German [ B1 ] Limited working proficiency 0 % Junior Mindset As a junior engineer, I complement my technical foundation with a proactive growth mindset and a strong commitment to continuous learning.  I approach every challenge with natural curiosity and resourcefulness, always seeking to understand the bigger picture while actively proposing solutions rather than just identifying problems.  Highly coachable and a strong believer in the power of collaboration, I thrive on constructive feedback and look forward to absorbing knowledge from experienced team members to deliver high-quality results quickly. Softwares I use Tools and Environment Cadence Virtuoso Practical experience in IC design and Layout using Cadence Virtuoso, ADE XL and Layout XL. ModelSim Used for testbench simulations and verifications of digital designs and RTL code. Linux shell Proficient in Linux command line for development, scripting, and system management. Git versioning Experienced with Git for version control, collaboration, and project tracking. VsCode IDE Boosts adaptability and efficiency by working across multiple languages in a single environment. Certificates Here are some of the certifications I have obtained, demonstrating my skills and commitment to continuous learning.  Click on the Box to see the Certificate. More are yet to come ! Python Certificate of Computer Science and Programming using Python: MIT’s edX online course Programming This certification highlights my ability to develop efficient and scalable solutions. IEEE Publication On-Chip Frequency-to-Voltage Conversion for Hardware Security Characterization. Programming The publication was produced with my colleague as part of an academic research project, where we designed a FVC from architecture to post-layout simulation on Cadence Virtuoso. TOEIC Certified in English proficiency through the TOEIC exam, demonstrating strong listening and reading comprehension skills. 915/990 This certification reflects my ability to communicate effectively in professional and international environments. Entrepreneuship Certification Certified through the « Les Entrep’  » program, validating key entrepreneurial skills such as teamwork, project management, and business

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