The goal of this project was to design, simulate, and implement the physical layout of a CMOS inverter using Cadence Virtuoso. The project was carried out on the AMS 0.35 µm (C35B4) technology node, providing hands-on experience with an industry-grade process design kit (PDK).
Project Workflow
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Schematic Design
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Built the inverter at the transistor level with NMOS and PMOS devices.
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Performed DC simulations to extract the Voltage Transfer Characteristic (VTC).
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Ran parameter sweep on MOS Width to optimize the inversion.
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Layout Implementation
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Designed the full custom layout of the CMOS inverter following AMS 0.35 µm design rules.
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Adjusted transistor sizing to balance performance and technology requirments.
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Verification
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Performed Design Rule Check (DRC) to ensure compliance with AMS design rules.
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Conducted Layout Versus Schematic (LVS) to confirm consistency between schematic and layout.
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Extracted parasitics (PEX) and ran post-layout simulations to evaluate performance degradation caused by layout effects.
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Used Tools
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Cadence Virtuoso for schematic, simulation (ADE XL) , and layout (Layout XL)
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AMS 0.35 µm (C35B4) CMOS technology
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SPICE simulations for electrical validation (DRC, and LVS)
Layout
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Layers MET1, POLY1, NDIFF, NPLUS
- Used DRM to ensure size and design constraints respect